This invention relates to a chopped Hall sensor circuit wherein the Hall-element exciting current is alternately switched from flow in one direction to flow in another direction, and more particularly relates to such a Hall sensor in which a chopped sample-and-hold Hall-voltage circuit is clocked synchronously with the switched Hall element.
It has long been common practice to excite a Hall element by connecting it permanently by two contacts to the DC supply voltage or other source of Hall current I.sub.H for obtaining a Hall voltage (V.sub.H) at two other contacts that is proportional to the product of the ambient magnetic field strength (B) and the Hall exciting current I.sub.h. When an ambient magnetic field is absent (zero strength), an unwanted off-set voltage (Vos) is typically produced at the Hall output contacts, and when the strength of an ambient field, B, is not zero, the Hall-element output voltage is the sum of V.sub.H and Vos. The magnitude and polarity of the unwanted off-set voltage are a function inter alia of stresses in the semiconductor chip of which it is formed, which stresses vary with mechanical pressure and temperature.
It is known to provide a switching circuit in which a Hall-element exciting current is alternately switched from flow in one direction to flow in another direction through the Hall element. Such a switching circuit is shown in FIG. 1. The symmetrical Hall element 10 has four equally spaced contacts 11, 12, 13 and 14 that define the corners of a hypothetical square 15. The contacts 11 and 14 are connected to the DC supply voltage, Vcc, via an electrically controllable single pole double throw switch 16 and the contacts 12 and 13 are connected to the supply voltage ground via an electrically controllable single pole double throw switch 18.
When the switches 16 and 18 are clocked by a high binary signal level during clock ck1 phase .phi.1, the Hall-element exciting current I.sub.H flows from contact 11 to contact 13. When subsequently the switches 16 and 18 are clocked by a binary signal low level during the next clock ck1 phase n.phi.1, the Hall-element exciting current I.sub.H flows from contact 14 to contact 12 in a direction through the Hall element that is at right angles to that which flowed during a phase .phi.1 of the clock signal ck1.
Switches 16, 18, 19 and 20 are shown (heavy arrow) in the positions corresponding to clock phase .phi.1. The other switch positions ((dashed arrows) correspond to clock phase n.phi.1. The periodic switching of direction of the Hall-element exciting current I.sub.H, as in the circuit of FIG. 1, combined with further signal processing makes it possible to greatly reduce the amount of the offset voltage Vos. The switching circuit output voltage V.sub.sH is composed of Vos and the wanted Hall voltage V.sub.H.
The clock signal ck1 alternately changes from phase .phi.1 to n.phi.1 as seen in FIG. 2a. In the switching circuit output voltage V.sub.sH, the Hall voltage component V.sub.H is positive during phase .phi.1 and negative during phase n.phi.1. During each phase, the magnitude of V.sub.H is I.sub.H xB. In the switching circuit output voltage V.sub.sH, this wanted component V.sub.H (FIG. 2c) appears combined with the unwanted off-set component Vos. The polarity of the unwanted off-set voltage component Vos in V.sub.sH is positive and essentially of the same magnitude during both phases .phi.1 and n.phi.1, as seen in FIG. 2b. The resulting switching circuit output voltage V.sub.sH is the sum of the two signals Vos and V.sub.H as shown in FIG. 2d.
During phase .phi.1, V.sub.sH =V.sub.H +Vos.
During phase n.phi.1, V.sub.sH =-V.sub.H +Vos.
Thus any circuit that will subtract the two voltage levels in the signal V.sub.sH, namely the level during phase n.phi.1 from that in phase .phi.1, will provide a difference voltage that is equal to just 2V.sub.H and the Hall off-set voltage has been theoretically eliminated.
A major problem in using a Hall switching circuit such as that of FIG. 1 is that the voltage spikes generated by the switching of the Hall exciting current I.sub.H tend to be very large compared to the Hall voltage V.sub.H so that expensive filter capacitors are required. The use of large low pass filter capacitors entails substantial expense and renders such circuits useless for measuring or detecting small level fast changing magnetic fields.
It has been suggested to solve this problem by use of a switching charge-transfer amplifier to amplify the Hall voltage and reduce the switching Hall spikes. However, charge-transfer circuits themselves introduce charge injection switching noise at the lowest Hall signal level in the system.
It is an object of this invention to provide a sensitive Hall sensor followed by an amplifier and a synchronously chopped sample-and-hold circuit providing dynamic off-set cancellation that is blind to Hall switch current voltage transients and to the characteristic off-set voltages both of the Hall voltage amplifier and the Hall plate without the use of input switching charge-transfer amplifier circuits.
It is a further object of this invention to provide such a Hall sensor in which the Hall voltage is amplified by a gain-chopped differential linear analog amplifier for blanking Hall-switching noise spikes.
It is yet a further object of this invention to provide such a Hall sensor in which the sample-and-hold circuit is a chopped cross-polarity sample-and-hold circuit that is fully differential for rejection of common mode noise signals.